This specification relates to polishing pads useful for polishing and planarizing substrates, including patterned wafer substrates associated with the manufacture of semiconductor devices.
The production of semiconductors typically involves several chemical mechanical planarization (CMP) processes. In each CMP process, a polishing pad in combination with a polishing solution, such as an abrasive containing polishing slurry or an abrasive-free reactive liquid, removes excess material in a manner that planarizes or maintains flatness for receipt of a subsequent layer. The stacking of these layers combines in a manner that forms an integrated circuit. The fabrication of these semiconductor devices continues to become more complex, requiring higher operating speeds, lower leakage currents and reduced power consumption. In terms of device architecture, this translates to finer feature geometries and increased metallization levels. These increasingly stringent device design requirements are driving the adoption of copper metallization in conjunction with new dielectric materials having lower dielectric constants. Unfortunately, the diminished physical properties, frequently associated with low k and ultra-low k materials, in combination with the devices' increased complexity have led to greater demands on CMP consumables, such as polishing pads and polishing solutions.
In particular, low k and ultra-low k dielectrics tend to have lower mechanical strength and poorer adhesion in comparison to conventional dielectrics that render planarization more difficult. In addition, as integrated circuits' feature sizes decrease, CMP-induced defectivity, such as, scratching, becomes a greater issue. Furthermore, integrated circuits' decreasing film thicknesses require improvements in defectivity while simultaneously providing acceptable topography to a wafer substrate—these topography requirements demand increasingly stringent planarity, dishing and erosion specifications.
For example, one source of gross defectivity with copper-low k wafers is delamination of low k dielectrics due to their poorer mechanical properties. In order to minimize such defectivity arising from delamination, there is a trend toward “gentler” polishing conditions, including lower polishing head down-force. Closely coupled with this trend is a belief that high friction between the wafer and pad increases defectivity. Unfortunately, it is often observed, however, that reducing friction unacceptably reduces polishing removal rates to commercially unacceptable rates.
Low k copper patterned wafers can show unacceptable levels of defectivity, but good topography with Rodel's IC1000™ series polishing pads. These pads consist of a porous polyurethane matrix with its porosity formed from polymeric microspheres. For example, James et al., in U.S. Pat. No. 6,454,634, disclose a porous polyurethane polishing pad with polymeric microspheres having improved stability, planarization and defectivity.
Unlike microsphere-containing pads, poromeric polishing pads consist of a “soft” resilient polymeric pad having porosity produced through a coagulation process. Although the poromeric pads achieve excellent defectivity, they lack the planarization ability demanded for CMP of low k and ultra-low k wafers. Generally, using a polishing pad giving good planarization sacrifices defectivity performance and using a polishing pad giving low defectivity sacrifices planarization performance. Thus, there is a demand for a polishing pad with an improved combination of properties to yield planarized wafers with low defectivity.